1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor device having multi-layer interconnection.
2. Description of the Related Art
Recently, the functions and processing speed of semiconductor devices have been enhanced so that the number of signal lines included in a multi-layer interconnection semiconductor integrated circuit contained in the semiconductor device has been increased. The number of interconnection layers in the multi-layer interconnection semiconductor integrated circuit may be added for increasing the number of signal lines in the multi-layer interconnection semiconductor integrated circuit. However, for suppressing the manufacturing cost, the number of the interconnection layers to be added is desired to be small.
In the case that an interconnection layer is additionally laminated (stacked) on a conventional multi-layer substrate, if the added interconnection layer has interconnections extending in the same direction as the interconnections formed in the interconnection layer laid immediately below, an interconnections formed in the added interconnection layer and an another interconnection formed in the interconnection layer laid below may overlap with each other in vertical direction, such as a first interconnection layer 10 and a second interconnection layer 20 as shown in FIG. 1. If the overlapping area between the interconnections in the interconnection layers adjacent to each other in the vertical direction is large, the coupling capacitance between the interconnections is also large, and the signals flowing through the respective interconnections have the effects of the couplings (electromagnetic couplings) on each other. As a result, noises are added to both of the signal lines, and erroneous operations are occurred in the semiconductor device having the multi-layer interconnection semiconductor integrated circuit.
For suppressing the coupling capacitance as mentioned above, a method is proposed in which the interconnections in an upper interconnection layer is arranged to be shifted by a half pitch from the interconnections formed in the lower adjacent interconnection layer. FIG. 2A shows the schematic sectional view of the interconnections, and FIG. 2B shows the planar view of the interconnections formed in the upper and lower interconnection layers from the top surfaces of the overlapping interconnection layers. In this method, since the coupling capacitance between the upper and lower interconnection layers are reduced, the noise contained in the signal transmitted through each interconnection is relatively reduced. However, even in the case of this method, as the length of the interconnection in the transmission direction of the signal is increased, the coupling capacitance as the multi-layer interconnection semiconductor integrated circuit becomes larger.
So, in order to further reduce the coupling capacitance in the multi-layer interconnection semiconductor integrated circuit, a method that enlarges the design value of the pitch between the interconnections formed in the same layer for both of the adjacent interconnection layers is proposed. FIG. 3A shows the schematic sectional view of the interconnections, and FIG. 3B shows the planar view of the interconnections formed in the upper and lower interconnection layers from the top surfaces of the interconnection layers. In this proposal, the coupling capacitance per unit length between the interconnections is further reduced as compared with those shown in FIGS. 2A, 2B. However, it is difficult to avoid the fact that as the length of the interconnection in the transmission direction of the signal is increased, the coupling capacitance of the multi-layer interconnection semiconductor integrated circuit becomes larger.
The following techniques are also disclosed.
In Japanese Laid Open Patent Application (JP-A-Heisei, 3-19257), a semiconductor integrated circuit device, in which a plurality of circuit blocks whose signal amplitudes are different are installed in a same semiconductor substrate is disclosed. In this semiconductor device, among signal interconnections for connecting between the circuit blocks, at least a part of the signal interconnections to transmit electric signals of small signal amplitudes is extended obliquely for the interconnection channel direction of the signal interconnection to transmit an electric signal of a large signal amplitude.
Also, a multi-layer interconnection semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-P 2001-168195A). The multi-layer interconnection semiconductor integrated circuit has an interconnection structure of at least 6 layers, wherein the interconnections of the first and second layers are formed on an orthogonal grid so as to be orthogonal to each other. Assumed that the unit pitch of the interconnections of the first and second layers are a, b, respectively, and n, m are even numbers of 2 or more, respectively, and an angle equal to arctangent (na/mb) is θ. Then, the interconnection of the third layer is formed on the oblique grid so as to be inclined in a +θ direction with respect to the interconnection of the first or second layer, and the interconnection of the fourth layer is formed on the oblique grid so as to be inclined in a −θ direction with respect to the interconnection of the first or second layer. And assumed that the unit pitch of the interconnections of the third and fourth layers are c, d, respectively, c=d=na×mb/{(na)2+(mb)2}½, and all of the intersections of the interconnections of the third and fourth layers are located at the positions overlapping with the intersections of the orthogonal grid of the interconnections of the first and second layers, and the interconnections of the fifth and sixth layers are formed on the roughly orthogonal grids constituting the partial sets of the orthogonal grids of the interconnections of the first and second layers. And assumed that the unit interconnection pitches of the fifth and sixth layers are e, f, respectively, e=na and f=mb, and all of the intersections of the interconnections of the fifth and sixth layers are located at the positions overlapping with the intersections of the inclination grids of the interconnections of the third and fourth layers.